1. Field of the Invention
The present invention relates to a charge coupled device having a bifurcated signal output path, and more particularly to a technique for improving the charge transfer efficiency.
2. Description of the Related Art
An example of the configuration of a general charge coupled device (CCD) having a bifurcated signal output path is shown in FIG. 11. FIG. 11 is a plan view of essential portions of the charge coupled device. In this charge coupled device, the signal output path is branched into two lines to alternately distribute and output signal charges, whereby the operating frequency of the circuit of a portion for outputting the signal is reduced to one-half.
In the drawing, reference numeral 7 denotes a first layer electrode, numeral 8 denotes a second layer electrode, and numerals 3 and 4 denote impurity regions below the respective electrodes (7 and 8). In addition, numeral 5 denotes a floating diffusion region (an impurity diffusion layer where the potential is not fixed; also referred to as FD1 and FD2), and numeral 9 denotes an output circuit.
As shown in the drawing, this charge coupled device (CCD) is formed such that electrodes which are driven by two-phase clocks H1 and H2 are arranged in a one-dimensional array, and the channel is branched into two lines at an end of the one-dimensional CCD. Electrodes of the CCD at the portion branched into two lines are respectively driven by two-phase clocks H3 and H4.
The electric charges transferred through the one-dimensional CCD are alternately distributed and outputted to respective CCD portions of the two lines as the electrodes on the branched CCD side are driven. Namely, the pair of floating diffusion regions 5 (FD1 and FD2) for detecting the transferred signal charge are respectively provided at ends of the two branch portions of the CCD, and the pair of output circuits 9 for detecting and outputting the potential change are respectively connected to the FD1 and FD2. Further, detection signals are outputted from signal output ends (OS1 and OS2) of the respective output circuits 9.
In addition, reset transistors (RS1 and RS2) for discharging the detected signal charge at a desired timing are respectively connected to FD1 and FD2. A common junction of the reset transistors (RS1 and RS2) serves as a reset drain (RD).
The CCD is of a two-phase drive type, and two-phase clocks are respectively imparted to the first layer electrodes 7 and the second layer electrodes 8. The channel immediately below the first electrode 7 is formed with a deeper potential than the channel immediately below the second layer electrode 8, and at the time of the transfer of the signal charge the signal charge is temporarily accumulated in the channel immediately below the first layer electrode 7.
The charge coupled device (CCD) having the configuration of FIG. 11 is described in, for instance, JP-A-5-308575. In the CCD of JP-A-5-308575, the electrodes after the branching of the channel are arranged from an electrode OG to FD. In the explanation of FIG. 11, it is assumed for convenience' sake that OG is set at a fixed voltage, and that controlling electrodes H3 and H4 are disposed therebetween. However, it is construed that control based on OG and control based on H3 and H4 in JP-A-5-308575 are equivalent.
Next, a description will be given of the operation this charge coupled device (CCD) with reference to a signal waveform diagram of FIG. 12 illustrating timings for driving the CCD.
φH1 and φH2 denote binary pulses of mutually opposite phases with a duty ratio of 50%, which are applied to the respective electrodes H1 and H2 in FIG. 11. φH3 and φH4 denote binary pulses of mutually opposite phases with a duty ratio of 50%, which are driven by frequencies in which φH1 and φH2 are divided into two, and which are applied to the respective electrodes H3 and H4 in FIG. 11.
φRS1 and φRS2 denote pulses of the same frequency as φH3 and φH4, but have a duty ratio of 25%. φRS1 corresponds to the rise of φH3, while φRS2 corresponds to the rise of φH4, and both φRS1 and φRS2 are respectively applied to the terminals RS1 and RS2 in FIG. 11.
FIGS. 13A and 13B are cross-sectional views, respectively taken along lines C-C′ and D-D′ in FIG. 11, illustrating the structure of these portions.
As shown in the drawings, an impurity layer 2 of an opposite conductivity type (P type) to that of a semiconductor substrate 1 of one conductivity type (e.g., N type) is formed on the obverse layer side of the semiconductor substrate 1, and the impurity layers 3 and 4 of an opposite conductivity type (N type) to that of the impurity layer 2 are formed on the impurity layer 2 on the obverse surface of the substrate 1. As for these impurity layers 3 and 4, the impurity layer 4 is relatively thinner than the impurity layer 3. In addition, a diffusion layer 5 is formed at a lateral end of the impurity layers 3 and 4.
The first layer electrodes 7 are formed on the semiconductor substrate 1 via an insulating layer 6, and the second layer electrodes 8 are respectively formed on both these first layer electrodes 7 and the substrate 1 via the insulating layers 6 and 6a. In addition, the impurity layer 3 is disposed below OG, and the impurity layer 3 is disposed below the first layer electrodes 7 as for below the other electrodes H1 to H4, while the impurity layer 4 is disposed below the second layer electrodes 8. The first layer electrode 7 and the second layer electrode 8 are electrically connected, as shown in FIG. 11, and are driven by the respective drive signals shown in FIG. 12, thereby realizing the operation of the known two-phase drive CCD.
Hereafter, a description will be given of the drive of the portion branched into two lines in the CCD.
FIG. 14 is a potential diagram of the C-C′ and D-D′ portions in FIGS. 13A and 13B during the period from the time t1 to the time t4 shown in the signal waveform diagram in FIG. 12.
As shown in the drawing, the signal charge transferred by the drive of the electrodes H1 and H2 is branched toward the two output terminals (OS1 and OS2) by controlling the drive of the electrodes H3 and H4. The drive period of the electrodes H3 and H4 is two times the drive period of the electrodes H1 and H2. For example, if it is assumed that the electrodes H1 and H2 are driven at 60 MHz, the electrodes H3 and H4 are driven at 30 MHz.
In the CCD shown in FIG. 11 and having the signal output path branched into two lines, when the charge is transferred from the CCD arranged in a one-dimensional array to the CCD at the portion branched into two lines, despite the fact that a long transfer time is required for it, it is, in reality, difficult to secure a sufficient transfer time, and the transfer efficiency declines for that reason.
Hereafter, a specific description will be given of this aspect.
FIG. 15 is a diagram schematically illustrating the manner of movement of the charge in a channel region for constituting the CCD shown in FIG. 11. FIG. 15 shows the manner of movement of the charge at a time t3 in FIGS. 12 and 14. It should be noted that, in the drawing, the charge is shown by “e.”
As shown in the drawing, in the one-dimensional CCD, the charge is transferred smoothly from the right side toward the left side in synchronism with the two-phase clock. However, the transfer of the charge from the channel region at the final end of the one-dimensional CCD to the channel region of the CCD at the portion branched into two lines does not suffice to merely transfer the charge from right to left, and the situation is different since the charge transfer distance inevitably becomes long.
Namely, in FIG. 15, although the charge is transferred to one branched (upper side) CCD, the charge is extensively distributed in the channel region (X) at the final end of the CCD which is arranged in the one-dimensional array and is adjacent to that branched CCD. In FIG. 15, the charge (e) at the lower portion in the drawing of that channel region (X) moves a long way toward the upper side in the drawing, and subsequently flows into the channel of the one branched (upper side in the drawing) CCD. Since the charge transfer time is determined by the potential and the transfer distance, the longer the transfer distance, the longer the transfer time.
Accordingly, if the time for transferring the charge to the CCD at the portion branched into two lines can be made sufficiently long, the transfer efficiency would improve. In reality, however, the charge transfer time is strictly regulated by the period of the two-phase drive, and it is impossible to make long only the time for transferring the charge to the CCD at the portion branched into two lines.
FIG. 16 is a timing diagram illustrating the detailed waveforms and phases, which are close to actual ones, of the respective transfer pulses shown in FIG. 12.
In FIG. 16, Tst1 and Tst2 denote periods of L and H of φH1 (periods of H and L of φH2), and Tsrf1 and Tsrf2 denote transition times. Meanwhile, Tpt1 and Tpt2 denote periods of H and L of φH3 (periods of L and H of φH4), and Tprf1 and Tprf2 denote transition times. In addition, Tsp3 and Tsp4 denote periods corresponding to Tst1 and Tst2.
In the period of t1 to t4 shown in FIG. 12, the charge transfer time in the channel below the electrodes (H1 and H2) is determined by Tst1 and Tst2 shown in FIG. 16. Namely, since the storage and transfer of the signal charge are repeated by the two-layer clocks φH1 and φH2, of the one-half period of φH1 (φH2), the portion (i.e., Tst1 and Tst2) excluding the transition times can be used as the effective transfer time.
Similarly, the time for transferring the charge from the electrode H1 adjacent to the electrodes H3 and H4 to the channel region below the electrodes (H3 and H4) is determined by Tsp3 and Tsp4. Namely, as the signal output path is branched into two lines to alternately distribute and output the signal charges, the operating frequency of the circuit of the portion for outputting the signal becomes one-half, alleviating the burden of the circuit associated with that portion. And yet, the charge transfer time is no different from the related-art example, and it is only Tsp3 and Tsp4 (=Tst1 and Tst2) of φH3 (φH4) that can be used as the effective transfer time.
Thus, in the transfer of charges to the CCD at the portion branched into two systems, extra time is inevitably required in light of the structure of the device, the actual time for transferring the charge is controlled by the frequency of the two-phase clock as in the related-art manner, and it is difficult to make the transfer time long. In this case, there can occur a situation in which the charge transfer fails to be completed within a predetermined transfer time, resulting in a decline in the charge transfer efficiency.
Accordingly, in a case where the CCD shown in FIG. 11 is used as, for example, a horizontal CCD of a solid-state imaging device in which photodiodes are arranged in a two-dimensional array, the drifting of an image and the deterioration of the resolution can possibly result. In addition, in the case of a solid-state imaging device in which a color filter is laminated on the photodiodes to obtain a color signal, there can be cases where a pseudo-color signal is generated, resulting in the deterioration of the image.